7/16/2023 0 Comments Xilinx ise 14.7 export netlistThis action triggered the synthesis and it's now more than 24 hours that ISE is trying to "Optimize" one of my module. Therefore, I tried to move to the next step adding a Time Constraint by double clicking on my top module -> User Constraints -> Create Timing Constraints in the ISE interface. The behavioural simulation (on Isim) takes a while but works perfectly. I just finished to write a pretty complete design on ISE 14.7 targetting a Virtex7 device.
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